Digital electronic devices, such as memory devices, communicate with external circuitry through input terminals, output terminals, and input/output terminals. These input/output terminals are bi-directional, i.e., digital input signals may be applied to the same terminal to which digital output signals are applied, although not at the same time. One type of input circuit to which input signals are initially applied is a digital differential receiver 10a, an example of which is shown in FIG. 1. The differential receiver 10a includes a pair of NMOS transistors 14, 16 having their sources coupled to a common node 20. The common node 20 is, in turn, coupled to ground through a NMOS current sink transistor 24 that is biased ON by coupling the gate of the transistor 24 to a suitable bias voltage. A pair of load impedances 30, 32 are coupled between the drains of the respective transistors 14, 16 and a power supply voltage VCC. The load impedances 30, 32 may be implemented by a variety of circuit components, such as resistors (not shown) or transistors (not shown). Differential output signals are generated at output nodes 34, 35 between the drains of respective transistors 14, 16 and the load impedances 30, 32. Alternatively, a single-ended output signal may be generated at either one of the output nodes 34, 35. The differential output signals or the single-ended output signal are applied to circuitry internal to an electronic device (not shown), such as a memory device.
The gate of one transistor 14 is coupled to a first input terminal 36, which is, in turn, coupled to a voltage reference source 40. The gate of the other transistor 16 is coupled to a second input terminal 38, which is, in turn, coupled to an externally accessible terminal 44a. As shown in FIG. 1, the reference voltage source 40 is also coupled to a plurality of other input receivers 10b, c . . . n that are coupled to respective extenially accessible terminals 44b, c . . . n. If the terminal 44a is also an output terminal, i.e., the terminal 44a is an input/output terminal, the terminal 44a is also coupled to the output of an output driver 50. An input of the output driver 50 is coupled to circuitry internal to an electronic device (not shown).
In operation, a digital input signal is applied to the gate of the transistor 16 through the terminal 44a. The magnitude of the input signal is compared to the magnitude of the reference voltage applied to the gate of the transistor 14. If the magnitude of the input signal is greater than the magnitude of the reference voltage, the output signal(s) are considered to be at one logic level. If the magnitude of the input signal is less than the magnitude of the reference voltage, the output signal(s) are considered to be at a different logic level.
One problem that is often encountered with the input receiver 10 of FIG. 1 results from noise signals present in the reference voltage. Noise signals momentarily increase or decrease the magnitude of the reference voltage, thereby altering the voltage at which a transition of the input signal from one logic level to another is detected. Consequently, the timing of transitions of the output signal from the input receiver 10 responsive to transitions of the input signal can vary in an unpredictable manner. An electronic device containing the input receivers 10 must therefore operate with looser timing tolerances, thereby reducing the operating speed of the electronic device.
Noise signals can be coupled to the reference voltage source 40 by several means. For example, Output signals from the output driver 50a can be coupled through the input receiver 10a to the reference voltage source 40. More specifically, since the transistors 14a, 16a will generally be biased to their conductive operating range, transitions of an output signal from the output driver 50a applied to the gate of the transistor 16a can be coupled to the common node 20a, and from the common node 20a to the gate of the transistor 14a. These noise signals resulting from the transitions of the output signal are then coupled to the gates of transistor 14b, c . . . n in the other input receivers 10b, c . . . n. One or more of these other input receivers 10b, c . . . n may be receiving an input signal via its respective terminal 44b, c . . . n at the same time the output driver 50a is applying an output signal to its respective terminal 44a. For example terminals 44b,c may be receiving signals corresponding to bits of an address at the same time the terminal 44a is outputting a signal corresponding to a bit of data. As a result, the timing with which these input receivers 10b, c . . . n respond to transitions of input signals can vary in an unpredictable manner.
The noise signals generated in this manner could be reduced significantly by providing each input receiver 10a, b, c, . . . n with its own dedicated reference voltage source 40, but doing so might significantly increase the size and cost of integrated circuits using such input receivers 10 because of the large number of terminals 44 typically provided for many integrated circuits.
There is therefore a need for a cost effective method and circuit for making digital differential input receivers 10 more immune to noise generated by respective output drivers 50 coupled to one or more of the terminals 44.